Impact of Data Sharing on CMP design: A study based on Analytical Modeling

In this work we study the effect data and instruction sharing on cache miss rates. We then extend an analytical system-level throughput model to take multi-threaded data and instruction sharing into account. We use the model to provide insights into the interaction of thread count, cache size, off-chip bandwidth, and, sharing, on system throughput. Using specific examples we teach how the model can reveal insights about the impact of sharing on questions such as 1) how should cores in a CMP be sized (fewer larger cores vs. more smaller cores); 2) how many and what configuration CMP chips should be used to build an SMP system given a total threadcount requirement; 3) how do system-level core, cache and bandwidth provisioning decisions change between multi-programmed workloads (as in a cloud computing context) and multi-threaded workloads (as in a commercial or scientific server). Our model reveals that the optimal number and size of cores in a CMP, and the optimal number of CMPs in an SMP, can be significantly different depending of the amount of sharing in the target workload.